1. Technical Field
This invention relates in general to electronic circuits and, more particularly, to digital signal processors.
2. Description of the Related Art
Despite the increasing speed of processors, some emerging applications like video conferencing, digital camera, and new standards in wireless communication supporting more efficient data communication, such as web browsing, will open up new services and therefore enormously increase the MIPS and parallelism requirement for devices. These applications might be executed in separate devices or combined together in the next generation of portable communicators. For these applications, low power consumption and short latency for real time operations are essential.
A single CPU solution with an integrated DSP function, which is the most appealing for the software development, does not seem to be the best trade-off in terms of power consumption and performance. Instead, a multi-processor architecture with heterogeneous processor including an MPU (micro-processor unit), one or several DSPs (Digital signal processors) as well as a co-processor or hardware accelerator and DMA provides significant advantages.
One shortcoming of DSPs is their memory I/O capabilities. Typically, the DSP has an internal memory upon which the DSP relies for storage of data and program information. While improvements in semiconductor fabrication have increased the amount of memory which can be integrated in a DSP, the complexity of the applications has increased the need for instruction and data memory even moreso.
In the future, applications executed by DSPs will be more complex and will likely involve multiprocessing by multiple DSPs in a single system. DSPs will evolve to support multiple, concurrent applications, some of which will not be dedicated to a specific DSP platform, but will be loaded from a global network such as the Internet. These DSP platforms will benefit from a RTOS (real time operating system) to schedule multiple applications and to support memory management to share and protect memory access efficiently between applications and operating system kernels.
Accordingly, a need has arisen for a DSP capable of sophisticated memory management.